Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and /CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1250 (mil)
Your Price: $59.00In Stock:
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